![]() Here we actually doing a bi-directional asynchronous communication between two FPGA board. There is no problem if you want to implement this using another board. But we barrowed that one from our laboratory for this project. Here we used a Used a Digilant Atlys FPGA development board with a Xilinx FPGA. For the project we were supposed to implement a UART link for a FPGA development board using Verilog as the HDL and send some data to another FPGA development board which also have a UART implementation. My group members are Chirath Diyagama, Isuru Nuwanthilaka and Dileepa Sandaruwan. This was a group project of four group members. ![]() This post is regarding a HDL implementation of a UART(Universal Asynchronous Receiver Transmitter) for one of our university fourth semester projects. UART Communication Link Implementation with Verilog HDL on FPGA Verilog Code for the Baud Tick Generator.UART Communication Link Implementation with Verilog HDL on FPGA.
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